1. Field of the Invention
The present invention relates to a programmable read-only memory cell having a channel layer arranged between a selection gate and a floating gate.
2. Description of the Related Art
In contrast to dynamic random access memory cells (DRAMs), programmable read-only memory cells according to the principle of a flash memory can retain the stored information even without an external power supply.
Conventional flash memories generally comprise a field-effect transistor (FET) having an additional floating gate, which is formed between the selection gate (control gate) of the FET and a channel layer which connects the two source/drain regions of the FET to one another.
In this case, in the programming mode of the memory cell, a specific charge is applied to the floating gate, which is insulated from its surroundings. The conductivity of the channel layer and thus the switching state of the FET are subsequently determined. A distinction is made between “normally on” and “normally off” memory cells depending on whether the charged floating gate closes or opens the channel of the FET. In this case, it is particularly simple to read a flash memory cell, since only the conductivity of the channel is checked for this purpose.
Despite these advantages over volatile memories, flash memories are not used ubiquitously. In particular, the significantly slower programming and erasing times of this type of memory compared with the programming and erasing times of volatile memories inhibit the spread of flash memory cells.
Furthermore, constructive problems arise in the case of combined memories, where, e.g., DRAM memory cells are also fabricated on a chip in addition to the flash memory cells, on account of the different technology sequence of the two memory cell types.
U.S. Pat. No. 6,052,311 entitled “Electrically Erasable Programmable Read only Flash Memory” and U.S. Pat. No. 6,011,288 entitled “Flash Memory Cell with Vertical Channels and Source/Drain Bus Lines” disclose flash memory cells with a reduced lateral extent. Both memory cells in each case have a floating gate formed in a trench between the source and drain regions of the respective memory cell and a selection gate arranged above the floating gate. In this case, the channels run below or laterally with respect to the floating gate.
JP 59 154071 A discloses a read-only memory. Similar read-only memories are described in JP 61 078169 A, U.S. Pat. Nos. 5,488,243, 6,252,275 and 6,248,626. U.S. Pat. No. 5,598,367 discloses an EPROM which utilizes a trench capacitor structure.